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ContactMPC857DSLVR50B
MPC8xx Microprocessor MPC8xx Series 357-BBGA
- Manufacturer: Rochester Electronics
- NO: 699-MPC857DSLVR50B
- Package: 357-BBGA
- Datasheet:
- Stock: 4810
- Description: MPC8xx Microprocessor MPC8xx Series 357-BBGA (Kg)
- Delivery:
- Payment:
In Stock
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| Parameters | |
|---|---|
| Voltage - I/O | 3.3V |
| Ethernet | 10Mbps (1), 10/100Mbps (1) |
| Number of Cores/Bus Width | 1 Core 32-Bit |
| Graphics Acceleration | No |
| RAM Controllers | DRAM |
| Additional Interfaces | I2C, IrDA, PCMCIA, SPI, TDM, UART/USART |
| Co-Processors/DSP | Communications; CPM |
| RoHS Status | ROHS3 Compliant |
| Package / Case | 357-BBGA |
| Supplier Device Package | 357-PBGA (25x25) |
| Operating Temperature | 0°C~105°C TA |
| Packaging | Tray |
| Series | MPC8xx |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Speed | 50MHz |
| Core Processor | MPC8xx |
MPC857DSLVR50B Description
The MPC862/857T/857DSL is a derivative of Freescale’s MPC860 PowerQUICC? family of devices. It is a versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. The MPC862/857T/857DSL provides enhanced ATM functionality over that of other ATM-enabled members of the MPC860 family.
MPC857DSLVR50B Features
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
– 16-Kbyte instruction cache (MPC862P) is four-way, set-associative with 256 sets; 4-Kbyte
instruction cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative
with 128 sets.
– 8-Kbyte data cache (MPC862P) is two-way, set-associative with 256 sets; 4-Kbyte data
cache (MPC862T, MPC857T, and MPC857DSL) is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
